中英
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logic block中文是什么意思
- 中文翻譯
- 造句
- 邏輯區(qū)段
- logic n. 1.邏輯，理論學(xué)。 2.推理[方法]；邏輯性，條理 ...
- block n. 1.片，塊，大塊；粗料，毛料；木料；石料；金屬塊； ...
- block configurable logic 可配置邏輯區(qū)塊
- block logic array 邏輯陣列區(qū)塊
- block logic computer 塊邏輯計算機
- block logic design 塊邏輯設(shè)計
- block, configurable logic (clb) 可配置邏輯區(qū)塊
- block, generic logic (glb) 通用邏輯區(qū)塊
- block, logic array (lab) 邏輯陣列區(qū)塊
- building block of logic 邏輯結(jié)構(gòu)圖
- built-in logic block observation 內(nèi)建邏輯模塊監(jiān)測
- builtin logic block observerr 內(nèi)置邏輯區(qū)塊監(jiān)察程序
- clb configurable logic block 可配置的邏輯塊
- configurable-logic block (clb) 可配置邏輯區(qū)塊
- flb functional logic block 功能邏輯塊
- functional logic block 功能邏輯部件
- generic logic block 基本邏輯單元; 通用邏輯區(qū)塊
- generic logic block (glb) 通用邏輯區(qū)塊
- glb generic logic block 普通邏輯塊
- lab logic array block 邏輯陣列塊
- lbd logic block diagram 邏輯方框圖
- lcb logic control block 邏輯控制塊
- logic array block (lab) 邏輯陣列區(qū)塊
- logic block addressing 邏輯塊地址
- logic block diagram 邏輯框圖
- Universal logic block
通用邏輯部件 - 5 sun x , xu j , trouborst p . testing xilinx xc4000 configurable logic blocks with carry logic modules . in proc
在我們的方法中，雖然tpg為cut生成了測試向量，但是配置成tpg的le可以進行自測試。 - Built - in self - test of logic blocks in fpgas finally , a free lunch : bist without overhead ! . in proc . vlsi test symp . ,
對于一個具有4輸入lut的fpga來說，這與lut測試需要8次配置形成了鮮明的對比。 - The low level layer of the system is composed of hardware drivers and hardware logic block implementation . furthermore , software emulation about this system based on high level computer languages is also covered
最后緊跟現(xiàn)代軟件測試方法的發(fā)展步伐,對所編寫的軟件進行測試,以保證在功能、性能、健壯性等方面能獲得良好的結(jié)果。 - The risc mcu core is based on harvard architecture with 14 - bit instruction length and 8 - bit data length and two - level instruction pipeline the performance of the risc mcu has been improved by replacing micro - program with direct logic block
設(shè)計的riscmcu采用14位字長指令總線和8位字長數(shù)據(jù)總線分離的harvard結(jié)構(gòu)和二級指令流水設(shè)計，并使用硬布線邏輯代替微程序控制，加快了微控制器的速度，提高了指令執(zhí)行效率。 - Base on the analysis of comparison to current file systems , this thesis proposes new distributed network file system architecture on the tcp / ip protocol . the newly proposed file system is a three - layer architecture including clients , index servers and logic block servers
本文在分析現(xiàn)有的網(wǎng)絡(luò)文件系統(tǒng)的基礎(chǔ)上，提出一種基于tcp ip的分布式網(wǎng)絡(luò)文件系統(tǒng)結(jié)構(gòu)，即以客戶端、索引服務(wù)器和邏輯塊服務(wù)器為基礎(chǔ)的三層結(jié)構(gòu)。 - Researched the methods to test configrable logic block ( clb ) and its sub - blocks . based on a “ divide and conquer ” methodology , the clb resources are divided into three basic blocks : logic units , carry logic module ( clm ) and lut ’ s ( look up tables ) ram - mode . the testing configurations are implemented based on a two - dimensional array structure for logic blocks
主要基于“分治法”對clb及其子模塊進位邏輯( clm ) 、查找表( lut )的ram工作模式等進行了測試劃分,分別實現(xiàn)了以“一維陣列”為基礎(chǔ)的測試配置和測試向量,以較少了測試編程次數(shù)完成了所有clb資源的測試。 - Through the implementing of kernel level file and cache mechanism at the client side , this newly proposed distributed network file system provides seamless network file access and reduces the performance decline caused by network transmission . utilizing the concept of logic block server , it provides the reliable data block storage and implements redundant storage capacity . utilizing the concept of the index server , it provide s the cost of the greatly for server and network during data access process and realizes the computing with balancing capacity
在客戶端通過實現(xiàn)內(nèi)核級文件的調(diào)用和緩沖機制，實現(xiàn)了文件的無縫網(wǎng)絡(luò)存取，并減少由于網(wǎng)絡(luò)傳輸帶來的性能下降的影響；利用邏輯塊服務(wù)器實現(xiàn)邏輯塊的冗余存取，實現(xiàn)數(shù)據(jù)塊的安全存放；利用索引服務(wù)器進行負載均衡計算，實現(xiàn)資料存取的較低網(wǎng)絡(luò)和服務(wù)器開銷；利用索引服務(wù)器實現(xiàn)服務(wù)器組的零管理，使該系統(tǒng)具有高效性、穩(wěn)定性和可伸縮性。 - However , in most published works , only the diagnosis of logic blocks is discussed . the diagnosis of fault routing network is considered in some cases , where switching matrices are diagnosed individually . an fpga usually consists of complicated routing structure , it may not be easy to apply tests to individually components
本文概述了已有fpga連線結(jié)構(gòu)的一些測試技術(shù)，結(jié)合以前的fpga的診斷與測試技術(shù)，提出了通過討論開關(guān)矩陣及其連線的一個可行的測試及診斷方法，由七個測試階段，分別討論了fpga開關(guān)矩陣中各開關(guān)與相關(guān)連線的各種可能發(fā)生故障的情況，通過施加相應(yīng)的測試信號序列來對連線資源的故障情況進行較完全的測試。 - The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length . the performance of mcu has been improved greatly by introducing single - clock - cycle instructions , setting multiple high - speed working registers and replacing micro - program with direct logic block etc . to keep the mcu core reusable and transplantable , the whole mcu core has been coded for synthesis in verilog hdl
該mcu核采用哈佛結(jié)構(gòu)、 16位指令字長和8位數(shù)據(jù)字長，通過設(shè)計單周期指令、在內(nèi)部設(shè)置多個快速寄存器及采用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執(zhí)行效率。
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